The present invention relates to a semiconductor device and, more particularly, to a shallow trench isolation type semiconductor device and a method of manufacturing the same.
Shallow trench isolation (STI) is commonly used to achieve device isolation in a manner so as to avoid the occurrence of a phenomenon referred to in the art as a xe2x80x9cbird""s beakxe2x80x9d phenomenon. For tight device isolation, the trench should be increased in length and width. As the integration level of semiconductor devices increases, the trench necessarily must decrease in width; which in turn, forces the trench to increase in depth to achieve proper isolation. Unfortunately, it is difficult for the trench depth to keep up with the trench width, as filling of the narrow and deep trenches is increasingly challenging.
Although operating a semiconductor device at a single voltage may be convenient, in some cases a high voltage may be applied to a portion of device in order to realize functions of a memory device such as EEPROM or flash memory. Since the portion of the device receiving the high voltage must have a voltage-resistant structure, a gate insulating layer in the high voltage region is relatively thicker, as compared to other regions.
FIG. 1 exemplarily illustrates a self-aligned flash memory device in which a polysilicon layer to compose a floating gate is partially formed prior to formation of a trench. In a cell area, an N-type well 105 and a P-type well 107 are formed on a P-type semiconductor substrate 110 to form a cell transistor. In a high voltage area, the transistor is formed in the P-type semiconductor substrate 110 for the purpose of forming a high junction resistor to a high voltage. To achieve tight device isolation, an ion implantation layer 109 for a channel stop is formed at a trench-formation region prior to formation of the trench. Preferably, a lower step of the trench is positioned to maximize ion concentration of the ion implantation layer 109. Gate insulating layers 120 and 121 are formed, and a polysilicon layer 130 is formed thereon. An etch protection layer 140, for trench etching, and a hard mask layer 145 are sequentially formed, for example silicon nitride and silicon oxide, respectively.
In the step of etching the trench area, as shown in FIG. 2, the hard mask layer 145, the etch protection layer 140, and the polysilicon layer 130 are sequentially etched. When the gate insulating layers 120 and 121 are then etched, the gate insulating layer 121 in the cell area becomes completely etched while the gate insulating layer 120 in the high voltage area remains to a thickness of 100 xc3x85-300 xc3x85 due to the relative difference in thickness of the gate insulating layers 120, 121 of the respective regions. If the trench is etched by targeting silicon of the substrate 100, the remaining gate insulating layer 120 operates as a mask. Thus, a trench is not formed, or is formed to be thinner than required, so that insulation provided by that trench may be poor.
In this regard, there is provided an applicable method wherein after removing the gate-insulating layer 121, a photoresist pattern 150 is formed to protect the cell area, and the remaining gate insulating layer 120 is removed by means of a silicon oxide etchant. If the etching is carried out without the photoresist pattern 150 by means of the silicon oxide etchant, the exposed gate insulating layer 120 is attacked around the trench in the cell area. This results in functional deterioration of the cell transistor. The gate insulating layers in the cell area and the high voltage area are thus removed by means of the etching, as shown in FIG. 3, in spite of the thickness difference.
Referring to FIG. 4, the substrate 110 in the trench area is etched by silicon etchant. An oxide layer for device isolation is stacked on the trench. By means of chemical mechanical polishing (CMP), the oxide layer is then removed to form a device isolation layer 155. For the tight insulation for high voltage operation, a trench width is preferably high and transistor concentration is preferably low.
Since the trench width is high and the transistor density is low in order to achieve tight insulation for high voltage operation, the trench depth is to be high during the step of etching a channel. In other words, an exposure step is additionally required for protecting the cell area and removing the remaining gate insulating layer of the high voltage area, and the trench etching speed is high. Therefore, a channel stop ion implantation layer 109 is almost removed, and therefore device isolation is weakened.
It is an object of the present invention to provide a shallow trench isolation (STI) type semiconductor device and method of forming such a device. which can simplify processing steps and achieve a tight device isolation in both a cell area and a high voltage area.
In one aspect, the present invention is directed to a shallow trench isolation type semiconductor device. A gate insulating layer is formed in a first region, for example a high-voltage region, and in a second region, for example a low-voltage region, the gate insulating layer being of greater thickness in the first region, relative to the thickness of the gate insulating layer in the second region. A shallow trench isolation layer is formed in the first region and the second region. The shallow trench isolation layer in the first region is thinner than shallow trench isolation layer in the second region.
The shallow trench isolation area in the first region is preferably thinner than that in the second region by approximately 100 xc3x85-900 xc3x85. An ion implantation layer for channel stop is preferably formed to overlap with a lower part of the shallow trench isolation layer, the depth of the ion implantation layer being identical in both the first region and the second region. The ion implantation layer is preferably a P-type impurity implantation layer. The gate insulating layer in the first region preferably has a thickness of 200 xc3x85-400 xc3x85, and the gate insulating layer in the second region preferably has a thickness of 70 xc3x85-100 xc3x85.
In another aspect, the present invention is directed to a shallow trench isolation type semiconductor device including gate insulating layers formed in a cell area and a high voltage area, the gate insulating layers being different in thickness in the cell area and high voltage area. A shallow trench isolation layer is formed in the cell area and the high voltage area, wherein the shallow trench isolation layer in the high voltage area is thinner than that of the cell area by 100 xc3x85-900 xc3x85. An ion implantation layer for channel stop overlaps with a lower part of the shallow trench isolation layer, wherein the combined depth of the ion implantation layer and the shallow trench isolation layer is equal in the cell area and the high voltage area.
In another aspect, the present invention is directed to a method of manufacturing a shallow trench isolation type semiconductor device. A gate insulating layer is formed in a first region and in a second region of a silicon substrate, the gate insulating layer being greater in thickness in the first region, as compared to the thickness in the second region. An etch protection layer is provided on the gate insulating layer. An etching mask pattern is formed to expose first and second trench regions, and the etch protection layer is masked using the etching mask pattern. The gate insulating layer is etched until the gate insulating layer in the second region is completely removed. The remaining gate insulating layer in the first region is then removed using an etchant wherein an etching selectivity of the substrate to the gate insulating layer is in the range of 1:1 to 3:1, to exposing the silicon substrate. The exposed silicon substrate is then etched in the first region for a predetermined time to form a trench for device isolation.
Preferably, first and second ion implantation layers for channel stop are formed through ion implantation prior to formation of the gate insulating layers on the substrate in the first and second regions, wherein the lower part of the trench is positioned in the body of a second ion implantation layer in the second region, and on a body of a first ion implantation layer in the first region.
Optionally, gate insulating layers of different thickness are formed in the second region and the first region, and a conductive layer is provided on the entire surface of the substrate prior to providing the etch protection layer.